The invention relates to exchanging pixel data among a plurality of pixel-processors in a computer graphics system.
In computer graphics an image is stored and processed electronically in a graphics processing subsystem and can be displayed on a cathode ray tube (CRT) monitor or printed at a printer. The image is often broken up into a two-dimensional array of pixels, which are the smallest addressable components of an image. A frame buffer is used to store pixel data indicating the states (e.g., color, intensity) of corresponding pixels, and the frame buffer is repeatedly accessed at a high rate (30 or 60 times per second) to display the image on the monitor. A pixel processor is used to create and process the pixel data stored in the frame buffer, and the pixel processor and frame buffer are controlled by the host computer, often in conjunction with other processors in the graphics processing subsystem.
In some graphics processing subsystems, the image is split up among a plurality of pixel-processors and associated frame buffers to speed up the processing of an image. In a parallel frame buffer architecture, the pixel array for the entire image is divided into a plurality of much smaller arrays (called cells) in which each pixel is assigned to a different pixel processor and associated frame buffer. E.g., in a 16-pixel processor arrangement having 4.times.4 cells, each cell is described by boundaries which occur every fourth pixel in the X-direction (from left to right of screen) and Y-direction (downward from top of screen). This permits simultaneous processing by the pixel processors when a small portion of the display is being processed at one time.
When modifying the displayed image, e.g., to move something shown in one portion of the display to another, so-called "bit-block" transfers (also referred to as "raster-ops") are used to transfer data from one frame buffer memory location (which corresponds to a particular screen location) to another. In the parallel frame buffer architecture, such bit-block transfers reguire movement of data from source pixel processors to destination pixel processors, the data being stored at the appropriate locations in the frame buffers associated with the destination pixel processors. Without such transfer between pixel processors, movements of pixel data are limited to movements along cell boundaries, e.g., every 4 pixels in the X and Y directions in a 4.times.4 arrangement.
One prior art method of transferring data between pixel processors involves sending the data to the host computer along a host bus and having the host computer then send the data to respective destination pixel processors. Another prior art method of transferring data between pixel processors involves providing a dedicated cache memory to receive the data being transferred from source pixel processors; the data are then forwarded to the destination processors.